GitHub

UART Design with CDC, FIFO Buffers, and Dynamic Baud Rate Configuration

This repository contains implementations of a UART (Universal Asynchronous Receiver/Transmitter) with Clock Domain Crossing (CDC), First In, First Out (FIFO) buffers, and dynamic Baud Rate ...
IEEE

Improved Power Transfer Efficiency Using a Dual Transmitter Receiver Design With Integrated Decoupling Coils for IPT EV Charging

Abstract: In high-power inductive power transfer (IPT) systems, multiple coils are used to enhance efficiency, but interactions between coils on the same side can reduce overall performance.
IEEE

Model Base Design of MIMO Transmitter and Receiver Implementation on an FPGA Board

Abstract: This paper describes the implementation of the MIMO transmitter and receiver on an FPGA: Zynq UltraScale + MPSoC ZCU102 FPGA board. An HW/SW co-design environment designed and implemented ...