GitHub

htminuslab/Modelsim-Python-Demo2

Demo showing Modelsim calling the Python's Numpy and Matplotlib libraries via the Foreign Language Interface (FLI). A VHDL testbench generates 2 sine waves with some added noise, the Numpy and ...
GitHub

htminuslab/Modelsim-Python-Demo1

Demo showing how to add a Python Constraint Solver to Modelsim This repository contains a simple FLI foreign subprogram example which calls a constraint solver written in Python. The demo shows how ...
IEEE

Design of high-precision FFT based on VHDL and analysis of code coverage

Abstract: This paper uses structured design to implement the floating-FFT by VHDL with ISE5.3 and simulates it by ModelSim. The data pathways in this project are in the form of 32-bit single precision ...
IEEE

A Methodology and Toolset to Enable SystemC and VHDL Co-simulation

Abstract: The new design challenges imposed by the increasing difficulties of today's electronic systems obligated designers to develop new methodologies. System-level design and platform-based design ...
TechRepublic

Design of Cache Memory with Cache Controller Using VHDL

The authors report on the design of efficient cache controller suitable for use in FPGA-based processors. Semiconductor memory which can operate at speeds comparable with the operation of the ...