EDN

Bringing MEMS into the IC design flow

Micro-electro-mechanical systems have been available for years, and have been successful in selected high-volume applications. But MEMS design is not as organized as it could be. MEMS design typically ...
Semiconductor Engineering

Secure Physical Design Roadmap Enabling End-To-End Trustworthy IC Design Flow

The FICS Research Institute (University of Florida) has published a new research paper titled “Secure Physical Design.” This is the first and most comprehensive research work done in this area that ...
Semiconductor Engineering

A Multi-Level Analog IC Design Flow For Fast Performance Estimation Using Template-Based Layout Generators And Structural Models

Analog IC design is a very challenging task as essential information is missing in the early design stages. Because the simulation of larger designs is exceedingly computationally expensive at lower ...
Design-Reuse

From Concept to Reality: Understanding the Cadence Analog IC Design Flow

Have you ever wondered how your smartphone can capture stunning photos, play crystal-clear music, or accurately measure your heart rate? The answer lies in the world of Analog Integrated Circuit (IC) ...
Business Wire

UMC and Cadence Collaborate on 3D-IC Hybrid Bonding Reference Flow

HSINCHU, Taiwan & SAN JOSE, Calif.--(BUSINESS WIRE)--United Microelectronics Corporation (NYSE: UMC; TWSE: 2303) (“UMC”), a leading global semiconductor foundry, and Cadence Design Systems, Inc.
EDN

TSMC outlines reference tool flow for 65-nm design

TSMC will announce this week a new reference IC design flow for its recently unveiled 65-nm process, with an emphasis on low-power design. Concurrently, the company will announce new DFM (design for ...