EDN

A tutorial on incremental design using FPGAs from Actel

Regardless of the amount of time and energy FPGA designers invest attempting to create “right-first-time” designs, the functional complexities, performance requirements, and high gate counts of large ...
EDN

Reducing FPGA Compile Time Using Parallel Compilation Methodology

Compile time for large designs has been a major bottleneck since FPGAs were first created. Reducing compile time offers a large benefit to users as their designs can be turned around quickly by ...
Electronic Design

Design Compiler Points Toward Better Physical Implementation

Synopsys' Design Compiler 2010 accounts for the challenges of modern physical IC design, offering floor plan exploration from within the synthesis environment. It also delivers physical guidance to IC ...
Design-Reuse

MOSAID Introduces Industry's First Double Data Rate (DDR) SDRAM Physical Interface (PHY) Compiler

OTTAWA, Ontario – May 22, 2007 - MOSAID Technologies Inc. (TSX:MSD), is demonstrating the industry's first DDR SDRAM PHY compiler at the Design Automation Conference (DAC) June 4-7 in San Diego. The ...
Electronic Design

System Compiler Speeds Front-End IC Design

Said to bring fully automated, accurate timing and block information to front-end integrated IC design, the TOPOMO physical system compiler integrates and automates block partitioning, block placement ...